mirror of
https://github.com/crystalidea/qt6windows7.git
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180 lines
9.3 KiB
Plaintext
180 lines
9.3 KiB
Plaintext
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# -*- mode: conf; indent-tabs-mode: t -*-
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# Feature CPUID function Bit Required feature
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#sep Leaf01EDX 11 # Sysenter/sysexit
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#cmov Leaf01EDX 15 # Conditional Move
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#clflush Leaf01EDX 19 # Cache-Line Flush
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#mmx Leaf01EDX 23 # Multi Media Extensions
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#fxsr Leaf01EDX 24 # FXSAVE instruction
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#sse Leaf01EDX 25 # Streaming SIMD Extensions
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sse2 Leaf01EDX 26 # Streaming SIMD Extensions 2
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# -- everything above this line is mandatory on x86-64 --
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sse3 Leaf01ECX 0 # Streaming SIMD Extensions 3
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#pclmul Leaf01ECX 1 # Carryless Multiply
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ssse3 Leaf01ECX 9 # Supplemental Streaming SIMD Extensions 3
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fma Leaf01ECX 12 # Fused Multiply-Add
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#cx16 Leaf01ECX 13 # Compare-Exchange 16 bytes
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sse4.1 Leaf01ECX 19 # Streaming SIMD Extensions 4.1
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sse4.2 Leaf01ECX 20 # Streaming SIMD Extensions 4.2
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movbe Leaf01ECX 22 # MOV Big Endian
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popcnt Leaf01ECX 23 # Population count
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aes Leaf01ECX 25 sse4.2 # Advenced Encryption Standard
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#xsave Leaf01ECX 26 # XSAVE, XGETBV instructions
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#osxsave Leaf01ECX 27 # XSAVE enabled by OS
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avx Leaf01ECX 28 # Advanced Vector Extensions
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f16c Leaf01ECX 29 avx # 16-bit Float Conversion
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rdrnd Leaf01ECX 30 # Random number generator
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#hypervisor Leaf01ECX 31 # Running on a hypervisor
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#fsgsbase Leaf07_00EBX 0 # FS/GS base access
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bmi Leaf07_00EBX 3 # Bit Manipulation Instructions
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#hle Leaf07_00EBX 4 # Hardware Lock Ellision
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avx2 Leaf07_00EBX 5 avx # Advanced Vector Extensions 2
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bmi2 Leaf07_00EBX 8 # Bit Manipulation Instructions 2
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#erms Leaf07_00EBX 9 # Enhanced REP MOVSB/STOSB
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#rtm Leaf07_00EBX 11 # Restricted Transactional Memory
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#rdt_m Leaf07_00EBX 12 # Resource Director Technology (RDT) Monitoring
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#mpx Leaf07_00EBX 14 # Memory Protection Extensions
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#rdt_a Leaf07_00EBX 12 # Resource Director Technology (RDT) Allocation
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avx512f Leaf07_00EBX 16 avx # AVX512 Foundation
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avx512dq Leaf07_00EBX 17 avx512f # AVX512 Double & Quadword
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rdseed Leaf07_00EBX 18 # Random number generator for seeding
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#adx Leaf07_00EBX 19 # Multi-Precision Add-Carry
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avx512ifma Leaf07_00EBX 21 avx512f # AVX512 Integer Fused Multiply-Add
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#clflushopt Leaf07_00EBX 23 # Cache-Fline Flush Optimized
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#clwb Leaf07_00EBX 24 # Cache-Line Write Back
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#avx512pf Leaf07_00EBX 26 avx512f # AVX512 Prefetch
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#avx512er Leaf07_00EBX 27 avx512f # AVX512 Exponential & Reciprocal
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avx512cd Leaf07_00EBX 28 avx512f # AVX512 Conflict Detection
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sha Leaf07_00EBX 29 # SHA-1 and SHA-256 instructions
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avx512bw Leaf07_00EBX 30 avx512f # AVX512 Byte & Word
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avx512vl Leaf07_00EBX 31 avx512f # AVX512 Vector Length
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avx512vbmi Leaf07_00ECX 1 avx512f # AVX512 Vector Byte Manipulation Instructions
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#pku Leaf07_00ECX 3 # Protection Keys for User mode
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#ospke Leaf07_00ECX 4 # Protection Keys Enabled by OS
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#waitpkg Leaf07_00ECX 5 # User-Level Monitor / Wait
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avx512vbmi2 Leaf07_00ECX 6 avx512f # AVX512 Vector Byte Manipulation Instructions 2
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shstk Leaf07_00ECX 7 # Control Flow Enforcement Technology Shadow Stack
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gfni Leaf07_00ECX 8 # Galois Field new instructions
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vaes Leaf07_00ECX 9 avx2,avx,aes # 256- and 512-bit AES
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#vpclmulqdq Leaf07_00ECX 10 avx # 256- and 512-bit Carryless Multiply
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avx512vnni Leaf07_00ECX 11 avx512f # AVX512 Vector Neural Network Instructions
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avx512bitalg Leaf07_00ECX 12 avx512f # AVX512 Bit Algorithms
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avx512vpopcntdq Leaf07_00ECX 14 avx512f # AVX512 Population Count
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#la57 Leaf07_00ECX 16 # 5-level page tables
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#rdpid Leaf07_00ECX 22 # RDPID instruction
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#cldemote Leaf07_00ECX 25 # Cache Line Demotion
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#movdiri Leaf07_00ECX 27 # Move Direct-store Integer
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#movdir64b Leaf07_00ECX 28 # Move Direct-store 64 bytes
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#enqcmd Leaf07_00ECX 29 # Enqueue Command
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#pks Leaf07_00ECX 31 # Protection Keys for Supervisor mode
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#avx5124nniw Leaf07_00EDX 2 avx512f # AVX512 4-iteration Vector Neural Network Instructions
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#avx5124fmaps Leaf07_00EDX 3 avx512f # AVX512 4-iteration Fused Multiply Accumulation
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#fsrm Leaf07_00EDX 4 # Fast Short REP MOV
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#uintr Leaf07_00EDX 5 # User interrupts
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#avx512vp2intersect Leaf07_00EDX 8 avx512f # AVX512 Intersection computation
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#serialize Leaf07_00EDX 14 # SERIALIZE instruction
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hybrid Leaf07_00EDX 15 # Hybrid processor
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#tsxldtrk Leaf07_00EDX 16 # TDX (RTM) Suspend Load Address Tracking
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#pconfig Leaf07_00EDX 18 # Platform configuration
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ibt Leaf07_00EDX 20 # Control Flow Enforcement Technology Indirect Branch Tracking
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#amxbf16 Leaf07_00EDX 22 amxtile # AMX Tile multiplication in BFloat16
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avx512fp16 Leaf07_00EDX 23 avx512f,f16c # AVX512 16-bit Floating Point
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#amxtile Leaf07_00EDX 24 # Advanced Matrix Extensions Tile support
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#amxint8 Leaf07_00EDX 25 amxtile # AMX Tile multiplication for Int8
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#avxvnni Leaf07_01EAX 4 avx # AVX (VEX-encoded) versions of the Vector Neural Network Instructions
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#avx512bf16 Leaf07_01EAX 5 avx512f # AVX512 Brain Float16
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#zlmovsb Leaf07_01EAX 10 # Zero-length MOVSB
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#fsrs Leaf07_01EAX 11 # Fast Short (REP?) STOSB
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#fsrc Leaf07_01EAX 12 # Fast Short (REP?) CMPSB, SCASB
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#fred Leaf07_01EAX 17 # Flexible Return and Event Delivery
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#lkgs Leaf07_01EAX 18 # Load into Kernel GS
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#lam Leaf07_01EAX 26 # Linear Address Masking
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#xsaveopt Leaf13_01EAX 0 # Optimized XSAVE
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#xsavec Leaf13_01EAX 1 # XSAVE with Compaction
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#xgetbv1 Leaf13_01EAX 2 # XGETBV with ECX=1
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#xsaves Leaf13_01EAX 3 # XSAVE Supervisor mode
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#xfd Leaf13_01EAX 4 # eXtended Feature Disable MSR
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#lzcnt Leaf80000001hECX 5 # Leading Zero Count
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# XSAVE states
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# Source: Intel Software Development Manual, Volume 1, Chapter 13
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# Source: Intel Instruction Set Extensions Manual (ed. 041), Chapter 3, "Intel AMX Instruction Set"
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# Grouping Value Required for
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xsave=X87 0x0001 # X87 and MMX state
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xsave=SseState 0x0002 sse # SSE: 128 bits of XMM registers
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xsave=Ymm_Hi128 0x0004 # AVX: high 128 bits in YMM registers
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xsave=Bndregs 0x0008 # Memory Protection Extensions
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xsave=Bndcsr 0x0010 # Memory Protection Extensions
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xsave=OpMask 0x0020 # AVX512: k0 through k7
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xsave=Zmm_Hi256 0x0040 # AVX512: high 256 bits of ZMM0-15
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xsave=Hi16_Zmm 0x0080 # AVX512: all 512 bits of ZMM16-31
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xsave=PTState 0x0100 # Processor Trace
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xsave=PKRUState 0x0200 pku # Protection Key
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# ??? 0x0400
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xsave=CetUState 0x0800 # CET: user mode
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xsave=CetSState 0x1000 # CET: supervisor mode
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xsave=HdcState 0x2000 # Hardware Duty Cycle
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xsave=UintrState 0x4000 uintr # User Interrupts
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# ??? 0x8000
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xsave=HwpState 0x10000 # Hardware P-State
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xsave=Xtilecfg 0x20000 # AMX: XTILECFG register
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xsave=Xtiledata 0x40000 # AMX: data in the tiles
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xsave=AvxState SseState|Ymm_Hi128 avx,fma,avx512f
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xsave=MPXState Bndregs|Bndcsr mpx
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xsave=Avx512State AvxState|OpMask|Zmm_Hi256|Hi16_Zmm avx512f
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xsave=CetState CetUState|CetSState shstk
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xsave=AmxState Xtilecfg|Xtiledata amxtile
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# Processor/arch listing below this line
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# Source: Intel Instruction Set Extension manual, section 1.2
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# Source: GCC gcc/config/i386/i386.h, i386-c.c, i386-builtins.c
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# Architecture Based on New features Optional features
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arch=x86_64 <> sse2
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# Core line
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arch=Core2 x86_64 sse3,ssse3,cx16
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arch=NHM Core2 sse4.1,sse4.2,popcnt
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arch=WSM NHM
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arch=SNB WSM avx
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arch=IVB SNB f16c,rdrnd,fsgsbase
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arch=HSW IVB avx2,fma,bmi,bmi2,lzcnt,movbe
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arch=BDW HSW adx,rdseed
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arch=BDX BDW
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arch=SKL BDW xsavec,xsaves
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arch=ADL SKL avxvnni,gfni,vaes,vpclmulqdq,serialize,shstk,cldemote,movdiri,movdir64b,ibt,waitpkg,keylocker rdpid
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arch=SKX SKL avx512f,avx512dq,avx512cd,avx512bw,avx512vl clwb
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arch=CLX SKX avx512vnni
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arch=CPX CLX avx512bf16
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arch=CNL SKX avx512ifma,avx512vbmi sha
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arch=ICL CNL avx512vbmi2,gfni,vaes,vpclmulqdq,avx512vnni,avx512bitalg,avx512vpopcntdq fsrm,rdpid
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arch=ICX ICL pconfig
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arch=TGL ICL avx512vp2intersect,shstk,,movdiri,movdir64b,ibt,keylocker
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arch=SPR TGL avx512bf16,amxtile,amxbf16,amxint8,avxvnni,cldemote,pconfig,waitpkg,serialize,tsxldtrk,uintr
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# Atom line
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arch=SLM WSM rdrnd,movbe
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arch=GLM SLM fsgsbase,rdseed,lzcnt,xsavec,xsaves
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arch=TNT GLM clwb,gfni,cldemote,waitpkg,movdiri,movdir64b
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# Xeon Phi line
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#arch=KNL SKL avx512f,avx512er,avx512pf,avx512cd
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#arch=KNM KNL avx5124fmaps,avx5124vnniw,avx512vpopcntdq
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# Longer names
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arch=Nehalem NHM # Intel Core i3/i5/i7
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arch=Westmere WSM # Intel Core i3/i5/i7
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arch=SandyBridge SNB # Second Generation Intel Core i3/i5/i7
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arch=IvyBridge IVB # Third Generation Intel Core i3/i5/i7
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arch=Haswell HSW # Fourth Generation Intel Core i3/i5/i7
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arch=Broadwell BDW # Fifth Generation Intel Core i3/i5/i7
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arch=Skylake SKL # Sixth Generation Intel Core i3/i5/i7
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arch=Skylake-Avx512 SKX # Intel Xeon Scalable
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arch=CascadeLake CLX # Second Generation Intel Xeon Scalable
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arch=CooperLake CPX # Third Generation Intel Xeon Scalable
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arch=CannonLake CNL # Intel Core i3-8121U
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arch=IceLake-Client ICL # Tenth Generation Intel Core i3/i5/i7
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arch=IceLake-Server ICX # Third Generation Intel Xeon Scalable
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arch=AlderLake ADL
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arch=SapphireRapids SPR
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arch=TigerLake TGL # Eleventh Generation Intel Core i3/i5/i7
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arch=Silvermont SLM
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arch=Goldmont GLM
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arch=Tremont TNT
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#arch=KnightsLanding KNL
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#arch=KnightsMill KNM
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