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https://github.com/crystalidea/qt6windows7.git
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49 lines
2.1 KiB
C++
49 lines
2.1 KiB
C++
// Copyright (C) 2022 Intel Corporation.
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// SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
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#include <immintrin.h>
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// Skylake AVX512 was added to GCC 4.9, Clang 3.7, and MSVC 2015.
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// Cannon Lake was added to GCC 5, Clang 3.8, and MSVC 2017 15.7,
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// so that's our minimum.
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// Ice Lake was completed with GCC 8, Clang 6, and MSVC 2017 15.8.
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int test(int argc, char **argv)
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{
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unsigned randomvalue;
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_rdrand32_step(&randomvalue); // RDRND (IVB)
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#ifndef __QNXNTO__ // buggy compiler is missing this intrinsic, but we allow it
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_rdseed32_step(&randomvalue); // RDSEED (BDW)
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#endif
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unsigned mask = _blsmsk_u32(argc); // BMI (HSW)
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int clz = _lzcnt_u32(mask); // LZCNT (HSW)
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int ctz = _tzcnt_u32(mask); // BMI (HSW)
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mask = _bzhi_u32(-1, argc); // BMI2 (HSW)
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__m128d d = _mm_setzero_pd(); // SSE2
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d = _mm_cvtsi32_sd(d, argc); // SSE2
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__m256d d2 = _mm256_broadcastsd_pd(d); // AVX (SNB)
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d2 = _mm256_fmadd_pd(d2, d2, d2); // FMA (HSW)
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__m128 f = _mm256_cvtpd_ps(d2); // AVX (SNB)
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__m128i a = _mm_cvtps_ph(f, 0); // F16C (IVB)
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__m128i b = _mm_aesenc_si128(a, a); // AESNI (WSM)
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__m128i c = _mm_sha1rnds4_epu32(a, a, 0); // SHA (CNL)
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__m128i e = _mm_sha1msg1_epu32(a, b); // SHA (CNL)
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__m128i g = _mm_sha256msg2_epu32(b, c); // SHA (CNL)
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__m512i zero = _mm512_setzero_si512(); // AVX512F (SKX)
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__m512i data = _mm512_maskz_loadu_epi8(mask, argv[0]); // AVX512BW (SKX)
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__m256i ptrs = _mm256_maskz_loadu_epi64(mask, argv); // AVX512VL (SKX)
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__m512i data2 = _mm512_broadcast_i64x4(ptrs); // AVX512DQ (SKX)
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__m256i data3 = _mm256_madd52lo_epu64(ptrs, ptrs, ptrs);// AVX512IFMA (CNL)
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data2 = _mm512_multishift_epi64_epi8(data, data2); // AVX512VBMI (CNL)
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return _mm256_extract_epi32(data3, 0); // AVX2 (HSW)
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}
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int main(int argc, char **argv)
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{
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return test(argc, argv);
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}
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